Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - SDRAM controller verilog

Search list

[Other resource] sdr_data_path

Description: SDRAM控制器Verilog员代码，数据链路模块，完成和顶层模块的数据交换-SDRAM controller member Verilog code, data link module, Top module completed and the data exchange
Platform: | Size: 1955 | Author: 陈建勇 | Hits:

[Other resource] Params

Description: SDRAM控制器Verilog员代码，设计参数模块，整个模块的所有参数定义-SDRAM controller member Verilog code, design parameter module, the entire module of all parameters defined
Platform: | Size: 849 | Author: 陈建勇 | Hits:

[Other resource] control_interface

Description: SDRAM控制器Verilog员代码，控制接口模块，完成和顶层模块的控制命令的传递-SDRAM controller member Verilog code control interface module, Top module and complete the transfer of control orders
Platform: | Size: 3410 | Author: 陈建勇 | Hits:

[Other resource] Commandinterface

Description: SDRAM控制器Verilog员代码，命令生成模块，完成SDRAM控制接口命令的生成-SDRAM controller member Verilog code, order generation module, SDRAM interface complete control orders Generation
Platform: | Size: 7694 | Author: 陈建勇 | Hits:

[Compress-Decompress algrithms] DDR2_sdram

Description: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Platform: | Size: 966656 | Author: 李国 | Hits:

[Embeded-SCM Develop] opb_psram_controller.tar

Description: opb接口sdram控制器源码，标准参考设计，verilog语言-OPB SDRAM controller source interface, the standard reference design, verilog language
Platform: | Size: 6144 | Author: 范俊 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: 已经验证可用。此代码为Verilog写的sdram的控制器，可以由用户的使用而加载到自己的项目中自行开发。-Have verified that is available. This Verilog code written sdram controller, can be loaded into the user' s use of their own self-developed projects.
Platform: | Size: 15360 | Author: lyd | Hits:

[VHDL-FPGA-Verilog] test

Description: Verilog HDL SDRAM controller
Platform: | Size: 3072 | Author: Jack | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_4Port

Description: 用Verilog写的SDRAM的控制器的代码，分为详细实现了对SDRAM的控制-Written using Verilog code for SDRAM controller is divided into in detail to achieve the control of SDRAM
Platform: | Size: 14336 | Author: feifei | Hits:

[VHDL-FPGA-Verilog] sdramc_controller

Description: sdram 控制器 用verilog语言实现 可综合-sdram controller can be integrated with the verilog language
Platform: | Size: 7168 | Author: alins | Hits:

[VHDL-FPGA-Verilog] verilog_sdram_controller_testbench

Description: SDRAM 控制器 ，Verilog版本的，带有完整的SDRAM 仿真模型，testbench等，能够实际使用，并且利于学习-The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with backannotated simulation at 125MHz
Platform: | Size: 309248 | Author: 严刚 | Hits:

[VHDL-FPGA-Verilog] sdram_vhdl

Description: DDR（双速率）SDRAM控制器参考设计verilog代码，可以直接用的，很好的。-DDR (double rate) SDRAM controller reference design Verilog code, can be directly used, very good.
Platform: | Size: 891904 | Author: 薛鹏展 | Hits:

[VHDL-FPGA-Verilog] memory-controller

Description: 存储控制器，包括CPUside，接口，MEMORY side三个部分，使用verilog语言-This represents the "memory controller" It runs with the assumption that it is being connected to PC100 SDRAM.
Platform: | Size: 8192 | Author: AricSnow | Hits:

[VHDL-FPGA-Verilog] sdram_mdl

Description: verilog实现SDRAM控制器，quartus工程-verilog SDRAM controller, quartus project
Platform: | Size: 2287616 | Author: 唐华 | Hits:

[VHDL-FPGA-Verilog] altera_sdram

Description: 基于quartus平台的sdram控制器设计（verilog 源码）-Based on the the quartus platform, the SDRAM controller design (Verilog source code)
Platform: | Size: 8762368 | Author: guotao | Hits:

[VHDL-FPGA-Verilog] my_test_rw_pack9

Description: 基于Verilog HDL的SDRAM控制器。 实验条件： 工具：Quartus II 6.0 ,SignalTap II FPGA：Altera Cyclone EP1C12Q240C8N SDRAM：HY57V283220T-6-SDRAM controller based on Verilog HDL. Experimental conditions: Tools: Quartus II 6.0, SignalTap II FPGA: Altera Cyclone EP1C12Q240C8N SDRAM: HY57V283220T-6
Platform: | Size: 3520512 | Author: TYS | Hits:

[VHDL-FPGA-Verilog] sdram_mdl

Description: 基于verilog的SDRAM读写控制,源自特权同学-SDRAM controller use to read or write base on verilog，it is from teqian
Platform: | Size: 2572288 | Author: gaopeng | Hits:

[VHDL-FPGA-Verilog] ddr2_v5

Description: 基于FPGA v5的ddr2-sdram控制器的设计verilog-Based on FPGA v5 of ddr2-sdram controller design verilog
Platform: | Size: 13487104 | Author: 铁鹏涛 | Hits:

[VHDL-FPGA-Verilog] 61EDA_C915

Description: altera公司的SDRAM 控制器的ip core源代码 里面包含verilog及vhdl两种语言编写的 方便选择-altera company SDRAM controller ip core source code which contains verilog and vhdl two kinds of language for easy selection
Platform: | Size: 2325504 | Author: 杜小方 | Hits:

[VHDL-FPGA-Verilog] sdram_verilog

Description: 基于verilog语言的SDRAM控制器-SDRAM controller based on verilog language
Platform: | Size: 6144 | Author: 黄易 | Hits:
« 1 2 3 4 56 »

CodeBus www.codebus.net